Task leads: Giovanni Petrucciani (CERN), Emilio Meschi (CERN)

We propose to develop the hardware architecture and the algorithms of a real-time analysis facility that would be operated at 40 MHz during HL-LHC. Leveraging external expertise on task-oriented optimization of heterogeneous computing environments, this task will operate a survey of hardware solutions to support a complete portfolio of physics analyses. To demonstrate real time analysis at 40MHz and benchmarks possible solutions, a test stand will be set up with FPGAs, servers hosting different accelerators and high-speed optical networking, connected to prototype CMS L1 trigger boards. As part of the project, a new data acquisition board for L1 scouting will also be developed, with higher input bandwidth and exploiting on the latest technologies (e.g. Xilinx Versal HBM, 400 GbE, …). This test stand will be used also for some of the R&D in T3.6 and T3.7.